Contents described in this section merely provide background information on the present embodiment and do not constitute the related art.
Recently, the sizes and operating voltage of electronic devices have been decreased due to high capacity, light weight, and high density tendencies of electronic products. Planar 2D mounting in the related art has limitations in solving a problem of an increased package area due to slow signal propagation and increased I/O pads.
In order to overcome the limitations, a three dimensional packaging method in which integrated circuits (ICs) are vertically stacked and mounted has attracted attention. Through silicon vias (TSV) are used, which are used as electrical paths by forming through holes in silicon wafers.
The through silicon vias may cause various defects. For example, in a process of forming the through silicon vias, there are a void defect which occurs because a conductive material cannot be completely filled in the through silicon vias, a bump contact fail which occurs as a semiconductor chip is bent or a bump material moves, a crack defect of the through silicon vias, and the like.
Since the through silicon vias serve as a medium for electrically connecting a plurality of semiconductor chips. Therefore, when the defect occurs, the through silicon vias cannot normally show a function as an electrode. In order to cope with such a case, there is a need for a repair technique for replacing a defective through silicon via with a normal through silicon via.